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SOC Verfication.Methodology and Techniques

  • Время публикации: 2018-12-12   Размер: 4311 Kb   Формат: PDF   загруженный: 29
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The design capacity that can be realized on a single integrated circuit (IC) at deep sub-micron (DSM) technology levels makes it feasible to integrate all major functions of an end product in a single system-on-a-chip (SOC). But the evolution to SOC design presents challenges to the traditional verification approaches.

This chapter addresses the following topics:

• Technology challenges
• Verification technology options
• Verification methodology
• Testbench creation and migration
• Verification languages
• Verification IP reuse
• Verification approaches
• Verification and device test
• Verification plans
• Example of a reference design

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