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  • Размер: 359 Kb Время публикации: 2018-12-10
    This chapter was established to address some of the concer and limitatio in the EIA-567 approach described in chapter 4. In order to keep things from getting too complicated, only sectio of code affected by the recommended or proposed change(s) will be shown. Once all such recommendatio have been introduced, a complete example model will be presented. It is worth noting that the generic driver and checker components provided in this chapter are original developments by the author. During the early stages of the TIREP project, the team did not have access to the variants developed byMr.Finegold for the F-22 model example. Functional variatio between these implementatio will be discussed in detail where appropriate.
  • Размер: 360 Kb Время публикации: 2018-12-10
    In the 1991/2 time frame, Mr. Len Finegold, working on an Air Force contract for the Computer Science Corporation, developed an example DID compliant VHDL model of a Viterbi Decoder. Mr. Finegold based his work upon the EIA-567 Commercial Component Specification. However, the packages and modeling approach.he developed have yet to be formally adopted by the EIA. The goal of EIA-567 modeling approach described herein, is to develop an Electronic Data Sheet for a component,sub-assembly, assembly or system using VHDL. Elements modeled in the EDS include input and output pin characteristics (including mimax operating currents, voltages, propagation delays and loads), timing cotraints (such as setup and hold times and/or mimax pulse widths), and operating point conditio (such as voltage, power,temperature, package type, radiation hardness, etc.)
  • Размер: 155 Kb Время публикации: 2018-12-10
    This chapter will provide some background to the modeling approach developed under the SHARP TIREP project. Additionally,it will addresssome ofthe recommended modeling conventio which have been established for use on the SHARP TIREP project. These conventioinclude file naming conventio and VHDL file header information. The conventio provided herein are recommendatio. Their use is not dictated by any of the standards or specificatio relating to VHDL. Selected Modules For the SHARP TIREP effort,the module selection of Table 2.1.2-1 was made. Module selection was based upon high use modules with current or expected near term obsolescence problems. All modules are the SEM format A configuration.
  • Размер: 191 Kb Время публикации: 2018-12-10
    Download A VHDL Modeling Guide 1 PDF at Jotrin Electronics. This document was developed under the Standard Hardware and Reliability Program (SHARP) Technology Independent Representation of ElectronicProducts (TIREP) project. It is intended for use by VHSIC Hardware Description Language (VHDL) design enginee and is offered as guidance for the development of VHDL models which are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be provided to manufacturing engineering peonnel for the development of production data and the subsequent production of hardware. Most VHDL modeling performed to date has been concentrated at either the component level or at the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under the SHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon low complexity Standard Electronic Modules(SEM) ofthe format A configuration. Although these modules are quite simple, it is felt that the lesso learned offer guidance which can readily be applied to a wide range of assembly types and complexities
  • Размер: 959 Kb Время публикации: 2018-12-10
    Download FPGA Design Process Guide PDF at Jotrin Electronics.For more help, please contact the technical team. The purpose of writing an FPGA design flow guide is to: 1. It is to standardize the entire design process and realize the rationality, coistency and efficiency of development. 2. Form a good and complete document. 3. Achieve smooth migration between different FPGA manufacture and from FPGA to ASIC. 4. Facilitate new employees to quickly master the design process of FPGAs in this department.
  • Размер: 1739 Kb Время публикации: 2018-12-10
    Download NIOSII complete tutorial& SOPC Bulider PDF at Jotrin Electronics.For more help, please contact the technical team.
  • Размер: 31 Kb Время публикации: 2018-12-10
    Download Writing VHDL for RTL Synthesis PDF at Jotrin Electronics.For more help, please contact the technical team. The name VHDL is representative of the language itself: it is a two-level acronym that stands for VHSIC Hardware Description Language; VHSIC stands for very high speed integrated circuit. The language is vast, verbose, and was originally designed for modeling digital systems for simulation.