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Дома > EDA/IC Design > How to break through the yield problem after the chip process reaches

How to break through the yield problem after the chip process reaches 3nm?

Время обновления: 2022-11-30 18:14:22


On July 25, 2022, SAMSUNG Electronics held a shipment ceremony for 3nm chip foundry products using the next-generation Gate All Around (GAA) transistor process node at the V1 production line (dedicated to EUV) in Hwaseong Park, Gyeonggi-do, South Korea.

Less than four months later, Korean media Naver broke the news that SAMSUNG's 3nm process yield is very low, less than 20%. And its 5nm and 4nm node yield problems are also delayed in improvement.

SAMSUNG Electronics has been working on the GAA transistor structure since the early 2000s. Since 2017, it has officially applied it to the 3nm process and announced the launch of the 3nm process mass production using GAA technology in June this year. It is the first foundry in the world to use the GAA transistor structure for wafer fabrication.

SAMSUNG Electronics reportedly approached Silicon Frontline Technology to seek help from this company to solve the yield problem. Progress is said to be good so far.

So, SAMSUNG Electronics has been spending more than 20 years on GAA, so why is the yield problem not solved after a long time? Where exactly does the problem lie?

Let's start with developing the transistor structure, the most basic unit of the chip, and then see what countermeasures are available.

The history of the development of transistor structure

A semiconductor chip is a collection of many transistors; a transistor is a small switch. A transistor represents a 0 or 1, also known as a bit.

The transistors used in processes above 20nm are called metal oxide semiconductor field effect tubes.

20nm to 3nm, finned FETs are used.

Below 3nm, fully encircled gate FETs are used.

Structural development of transistors.png
Structural development of transistors

Why has it evolved so much? Mainly because of the working principle of transistors, within the transistor, scientists defined the concept of Gate Length, which is the direction of electron flow, and its short side is the process.

The principle is that a voltage is applied to the metal gate to control the conduction and shutdown of electrons. If the electrons can conduct through, it means 1, and if they turn off, it means 0.

This switch is to rely on the gate to apply voltage to cause the electric field to control, but the main impact of the electric field is the contact surface. If the gate length is made smaller and smaller, the pink contact area will be smaller and smaller. When small to a degree, to close the electron will not be able to close. The electrons that can't be locked will sneak through.

FinFET Transistor Working Principle.png
FinFET Transistor Working Principle

As a result, the leakage current becomes larger in the advanced process.

Comparison of NMOS transistor structure in switching form: When a voltage is applied to the gate to turn on the transistor, the current flows from the high-voltage drain to the low-voltage source.

The solution to this problem is to increase the contact area between the gate and the electron channel. The larger the contact area, the better the control effect. So to 20nm below the change to finFET transistors, adding voltage becomes pink. This part of the area is increased to improve the effect. The electric field is stronger, can lock the electrons, and will not leak.

To 3nm below, it is too small, and the contact area is insufficient. How to do?

Only up and down, left and right, all together to wrap it up, with the gate to wrap up the electronic channel, became the GAAFET so that the control effect would be better.

For now, every wafer foundry is probably using this way to make.

The yield problem is low what to do?

SAMSUNG Electronics, this time before TSMC launched the 3nm process, but the situation is not better. The yield rate is less than 20%, which is a bit expensive. In addition to the previous, yield cannot be improved due to the 4nm and 5nm process, and let the big customers Qualcomm and Nvidia and other large customers to single TSMC. Big customers may be lost if the yield problem is not solved this time.

To better solve the yield problem, SAMSUNG Electronics has approached the manufacturer Silicon Frontline Technology to help them improve the yield of the 3nm GAA structure.

According to Silicon Frontline Technology's website, the company is located in San Jose, California, and provides semiconductor design and verification solutions.

The company provides guaranteed accurate and guaranteed fast resistance, capacitance, ESD, and thermal analysis for post-layout verification, and its products have been used by more than 70 customers, including 12 of the top 25 semiconductor suppliers worldwide, are recognized and used by leading foundries, and have been used in more than 500 designs. And customers have used their technology to solve problems in 10nm, 14nm, 28nm, 40nm, ADCs, Serdes, sensitive analog circuits, image sensorsmemories, custom digital designs, and power devices.

Their main experience lies in providing wafer fabs with electrostatic discharge (ESD) prevention technology, which is a major cause of defects in the wafer production process and is known to be one of the major reasons for the low yield of SAMSUNG's 3nm GAA technology.

Silicon Frontline Technology has been using water quality and electrostatic discharge (ESD) prevention technology to reduce defects in the production process and improve wafers' yield.

Although SAMSUNG claims to have obtained positive results by integrating the technology used by its partners, the actual results need to be continuously observed in the coming months.

Currently, more than 90% of the failure analysis done in the market is caused by electrostatic discharge. According to the electrical test results, the failure mode contains an open circuit, short circuit or leakage, parameter drift, functional failure, etc.

According to the cause of failure, the failure modes can be classified as electrical overstress, failure due to electrostatic discharge, failure due to poor manufacturing process, etc.

How is electrostatic discharge generated?

During the manufacturing process of the chip, electrostatic discharge may occur between the semiconductor device and the metal layer on the chip during the manufacturing process.

Electrostatic discharge failure can be attributed to two scenarios: first, the electrostatic discharge acts directly on the chip; second, the electrostatic discharge interferes with the normal operation of the equipment produced or interferes with the external circuit environment.

Charge-induced damage.png
Charge-induced damage

The above figure is Charge Induced Damage (CID, Charging Induced Damage) when the chip in the production process and semiconductor equipment contact or proximity may produce charge-induced damage. This figure is an electrostatic photo that broke the wafer surface. A closer look at the magnification reveals that it is actually a transistor inside that was damaged. If you look closely with a microscope, you will find that this one IC is beaten up.

Profile view of a broken wafer1 .png

The picture above represents a broken by static electricity. Looking from the side, you will find that the multilayer metal wire, when the phenomenon of electrostatic breakdown occurs, this place will have defects. At this time, the chip is broken.

Profile view of a broken wafer2.png

Analysis can be found in certain locations on the wafer, especially prone to electrostatic discharge damage to the chip. For example, the red dot shown above is the laboratory. The researchers measured in a certain condition, certain locations are prone to damage the chip.


SAMSUNG has been experiencing yield problems, so this time, they want to use the electrostatic discharge simulation software provided by Silicon Frontline Technology to help them find the cause and then solve the yield problem. If they can successfully solve the yield problem this time, they will be able to surpass TSMC in the future advanced process competition.

After all, TSMC's current 3nm process is still using FinFET technology, and they will only use GAAFET technology by 2025 at 2nm. And if SAMSUNG solves the yield problem this time, it will have 3 more years of practical experience than TSMC when it comes to 2nm competition. Therefore, the dueling point between the two companies should be after 2025.

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