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Дома > Other > Comparison of Verilog HDL and VHDL Languages

Comparison of Verilog HDL and VHDL Languages

Время обновления: 2021-08-02 11:33:21

Both Verilog HDL and VHDL are hardware description languages for logic design, and both have become IEEE standards; VHDL became an IEEE standard in 1987, and Verilog HDL became an IEEE standard in 1995.


VHDL became an IEEE standard before Verilog HDL because VHDL was developed by a U.S. military organization, while Verilog HDL was converted from the private property of a common civilian company.


VHDL's full English name is VHSIC Hardware Description Language, and VHSIC is the abbreviation of Very High Speed Integrated Circuit, meaning very high speed integrated circuit, so the accurate Chinese translation of VHDL is very high speed integrated circuit hardware description language.


1.Verilog HDL and VHDL common points


Verilog HDL and VHDL as a language for describing hardware circuit design, their common features are.


- Ability to abstractly represent the structure and behavior of a circuit formally.


- Supports the description of hierarchies and domains in logic design.


- The ability to simplify the description of circuits by borrowing the sophisticated structure of high-level languages.


- Circuit simulation and verification mechanisms to ensure the correctness of the design.


- Supports comprehensive conversion of circuit descriptions from high level to low level.


- Hardware description is independent of the implementation process (process parameters can be included through properties provided by the language).


- Easy documentation, understanding and design reuse.

Differences between Verilog HDL and VHDL.png


2. Differences between Verilog HDL and VHDL


However, Verilog HDL and VHDL each have their own characteristics.


Since Verilog HDL was introduced as early as 1983, Verilog HDL has a broader design community and far more mature resources than VHDL.


Compared with VHDL, the biggest advantage of Verilog HDL is that it is a very easy to master hardware description language. With a basic programming foundation in C, this design technique can be mastered in two to three months through twenty hours of study and a period of practical operation.


The mastery of VHDL design technology is more difficult. This is because VHDL is not very intuitive and requires a foundation in Ada programming.


The current versions of Verilog HDL and VHDL also differ in the coverage of behavioral level abstract modeling. Verilog HDL is generally considered to be slightly worse than VHDL in terms of system-level abstraction, and much better than VHDL in terms of gate-level switching circuit description.


Basic structure of Verilog HDL programs


Verilog HDL is a language for digital logic circuit design. A circuit design described in Verilog HDL is the Verilog HDL model of that circuit.Verilog HDL is both a language for behavioral and structural description. That is, both the functional description of the circuit and the components and their connections can be used to build the Verilog HDL model of the designed circuit. the Verilog model can be different levels of abstraction of the actual circuit. These levels of abstraction and their corresponding model types are of the following five types.


- System level (System): A model that implements the external properties of the designed module in a high-level language structure.


- Algorithm Level (Algorithm): A model that implements the design algorithm in a high-level language structure.


- RTL Level (Register Transfer Level): A model that describes the flow of data between registers and how to handle them.


- Gate-Level: A model that describes logic gates and the connections between logic gates.


- Switch-Level: A model that describes the triode and storage nodes in a device and the connections between them.


A complete Verilog HDL model of a complex circuit system is composed of several Verilog HDL modules, each of which can be composed of several sub-modules. Some of these modules need to be synthesized into specific circuits, while others are simply existing circuits or excitation sources that interact with the modules designed by the user. Using this capability provided by the Verilog HDL language structure, it is possible to construct a clear hierarchy between modules to describe extremely complex large designs and to perform rigorous verification of the logic circuits designed.


As a structured and procedural language, the syntactic structure of the Verilog HDL behavioral description language is well suited for algorithm-level and RTL-level model design. This behavioral description language has the following capabilities.


- The ability to describe program structures for sequential execution or parallel execution.


- Explicitly control the start time of processes with delay expressions or event expressions.


- Triggers activation behavior or stopping behavior in other processes by named events.


- Provides conditional, If-Else, Case, and loop program structures.


- Provides Task program structure with parameters and non-zero duration.


- Provides function structures that can define new operators.


- Arithmetic, logical, and bitwise operators for building expressions are provided.


- The Verilog HDL language as a structured language is also well suited for gate-level and switch-level model design. Because of its structured nature it in turn has the following features.


- Provides a complete set of combinatorial primitives (Primitive).


- Provides Primitives for bidirectional pathways and resistive devices.


- Charge sharing and charge decay dynamics of MOS devices can be modeled.


The constructive statements of Verilog HDL can accurately model the signals. This is because in Verilog HDL, delay and output strength primes are provided to model signals with a high degree of accuracy. Signal values can have different intensities, and the effect of uncertain conditions can be reduced by setting a wide range of fuzzy values.


Verilog HDL, as a high-level hardware description programming language, has a C-like style. The If statement, Case statement, etc. are very similar to the corresponding statements in C language. If the reader has already mastered the foundation of C programming language, it is not difficult to learn Verilog HDL. As long as the reader focuses on understanding the special aspects of certain statements of Verilog HDL and strengthens the hands-on practice, he can master it well and use its powerful functions to design complex digital logic circuits. The following will introduce the basic structure and syntax in Verilog HDL.


Adders


Module Adder ( Count,Sum,A,B,Cin ); //  Adder module port declaration


Input [2:0] A,B; //port description

Input Cin;

Output Count;

Output [2:0] Sum;

Assign {Count,Sum} = A + B + Cin; //Adder algorithm implementation

Endmodule


This example describes a three-digit adder called Adder that computes Sum and Count from two three-bit numbers A, B and the integer Cin. The example shows that the entire Verilog HDL program is nested within the Module and Endmodule declaration statements.


Comparators

Module Compare (Equal,A,B); //Comparator module port declaration

Output Equal; //output signal Equal

Input [1:0] A,B; //Input signals A, B

Assign Equal=(A==B)?1:0; //If the two input signals A and B are equal, the output is 1, otherwise it is 0

Endmodule


This program describes a comparator called Compare with consecutive assignment statements. It compares two bits A and B. If A and B are equal, the output Equal is high, otherwise it is low. In this program, "/*........ */" and "//........." indicate the comment part, the comment is only for the programmer to understand the program, it does not work for compilation.


Use the tristate driver of the original language.


Module Trist2(Out,In,Enable); //Tri-state initiator module port declaration

Output Out; //Port declaration

Input In, Enable;

Bufif1 Mybuf(Out,In,Enable); //Instantiate the macro module Bufif1

Endmodule


This example describes a three-state driver called Trist2. The program implements its function by calling an existing tristate driver instance component Bufif1 in the Verilog language library


A self-designed tristate driver.

Module Trist1(Out,In,Enable); //Tri-state initiator module port declaration

Output Out; //Port description

Input In, Enable;

Mytri Tri_inst(Out,In,Enable);//Instantiate Tri_inst, an instance component defined by Mytri module

Endmodule

Module Mytri(Out,In,Enable); //Tri-state initiator module port declaration

Output Out; //Port declaration

Input In, Enable;

Assign Out = Enable? In : ''Bz; //Tri-state initiator algorithm description

Endmodule


This example describes a tri-state gate in a different way. There are two modules in this example. The module Trist1 calls the instance component Tri_inst defined by the module Mytri. module Trist1 is the top-level module. Module Mytri, on the other hand, is referred to as a submodule.


As you can see by the above example.


- Verilog HDL programs are composed of modules. The content of each module is nested between the Module and Endmodule statements. Each module implements a specific function. Modules can be nested hierarchically. Because of this, it is possible to divide a large digital circuit design into smaller modules to achieve a specific function, and finally the top-level module calls the sub-modules to achieve the overall function.


- Each module has to be defined with a port definition and description of the input and output ports, and then the function of the module is described logically in terms of behavior.


- The Verilog HDL program can be written in a free format, with several statements in one line, or multiple lines in one statement.


- Except for the Endmodule statement, each statement and data definition must have a semicolon at the end.


- You can use "/*..... */" and "//......." to comment any part of the Verilog HDL program. A good, usable source program should be annotated as necessary to enhance readability and maintainability.


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