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Дома > Programmable logic > Programmable logic device and ASIC comparison introduction

Programmable logic device and ASIC comparison introduction

Время публикации: 2020-09-26 14:04:54

Early electronic system hardware design uses discrete components. With the emergence and application of integrated circuits, people choose standard integrated circuits with fixed functions (such as various logic gates, encoders, decoders, flip-flops, and counters, etc.) to form hardware systems Later, the microprocessor was used as the core to form the system. Nowadays, application-specific integrated circuits (ASIC) are widely used to form the system. A complex digital system can be realized by only one or several ASICs.

There are roughly two methods of making ASICs. One is the mask processing method (mask processing is a manufacturing process of IC, which means that different positions on the wafer need to be processed at different stages of IC manufacturing, which requires masking other The parts that do not need to be processed are called different mask layers), which are manufactured by semiconductor manufacturers; the other is realized by field-programmable devices. Users can use computers and EDA development tools to design circuits or systems. "Programming" on the chip, you can get an ASIC.

1、Programmable logic device

Programmable logic device.jpg

Programmable logic device (PLD) is a digital integrated circuit that can be defined and set by the user and belongs to programmable ASIC. There are many types of PLDs. The PLD devices that are currently widely used are mainly complex programmable logic devices CPLD and field-programmable gate array FPGAs.

The CPLD device contains many logic blocks and wiring resources. The logic blocks are composed of AND-OR arrays and flip-flops. The functions of the logic blocks are determined by user programming. Between logic blocks, logic blocks and the outside of the chip can realize information exchange through programmable wiring resources. Usually, CPLD devices are made with the COMS E2PROM process, and when the user's logic is written, it will not be lost even if power is off. Usually, the CPLD also integrates E2PROM, FIFO, or dual-port RAM to adapt to the design of digital systems with different functions.

FPGA is another type of programmable logic device, which is very different from CPLD in structure. The circuit design is not restricted by the two-level combinational logic of the AND-OR array structure. The chip is mainly composed of many programmable logic modules, which are connected by crisscrossing distributed programmable interconnect lines to form extremely complex logic circuits. It is more suitable for the realization of multi-level logic functions and has a higher integration density and application flexibility. At present, there are mainly two types of FPGAs based on COMS SRAM technology and FPGAs based on anti-fuse technology. Since data in SRAM can theoretically be written infinitely, an FPGA based on SRAM technology can be programmed for unlimited times. However, SRAM has the characteristic of data volatility, that is, its original logic function will disappear when the power is off. Therefore, when using this type of FPGA, a PROM is required to save the programming data. After power on, the FPGA will first read the programming data. Initialize, and then start to work normally. FPGAs based on anti-fuse technology can only be programmed once. This type of FPGA is more suitable for finalized products and mass applications.

A programmable logic device is an ideal device for composing a digital logic system. It can realize various logic functions only by defining the logic and output/input pins inside the device during design. Moreover, due to the flexibility of defining pins, it greatly reduces The workload and difficulty of the circuit diagram, and circuit board design effectively increases design flexibility and improves work efficiency. Compared with ASIC, the disadvantage of this method is that the single-chip cost is higher, and the performance of the circuit is limited by the PLD device, and it is difficult to achieve high performance or design with special requirements.



ASIC chips are mainly manufactured by semiconductor manufacturers using a semi-custom method and commonly used are gate arrays and standard cells. The internal structure of the gate array and the standard cell is different, and the manufacturing technology used is different, so their cost, production time, and efficiency are also different.

Gate array is an integrated circuit design technique that uses mask programming. Gate array technology includes CMOS gate array, emitter-coupled logic (ECL) gate array, BiCMOS gate array, digital, and analog compatible gate array. Semiconductor manufacturers prepare a regular array of logic gates or components on the chip in advance and process them until a process before the interconnection line lithography. Such semi-finished chips are called gate array masters. Then, according to the customer's request, the manufacturer designs the interconnection layout and performs plate making and photolithography processing, and the chip becomes an application-specific integrated circuit that meets the user's requirements. Therefore, the gate array master can be mass-produced, and it can be adapted to the requirements of multiple varieties only by changing the interconnection line layout. Usually, the process level of programming is limited to the last interconnection line (single or multilayer wiring level). The advantages of gate array design technology are short cycle, low cost, high success rate, and good reliability; but there are also disadvantages such as insufficient design flexibility, low gate utilization, and high power consumption.

The standard unit is a semi-custom chip that is currently used more frequently. Semiconductor manufacturers have pre-designed unit circuits with certain logic functions (such as flip-flops, adders, counters, RAMs, etc.), and the layout of these unit circuits has been completed. After strict testing, the logic functions and good timing can be guaranteed The function is then provided to the designer in the form of a standard cell library. ASIC designers can connect these units with certain functions together to realize the required functions, just like when a printed circuit board designer connects logic devices with specific functions on the PCB. Of course, designers need to use the placement and routing tools provided by semiconductor manufacturers to place and route these logic units on the wafer in the most optimized manner possible.

Unlike gate arrays, although these standard logic cells have been pre-designed, they are not placed on the chip in advance (because the manufacturer does not know the designer’s design in advance, there is no universal way to determine the use of various logic cells Quantity and specific placement). Therefore, the standard cell design has no concept of a master. Each wafer is made temporarily according to the designer's needs, and the most basic transistors inside the wafer are carved on-site. Therefore, the production cycle of standard logic cells is longer than that of gate arrays. Since each layer of the mask of the standard cell is customized according to the needs of different users, users cannot share the development cost, so the trial production cost of the standard cell ASIC is higher than that of the gate array ASIC.

The advantages of the standard cell structure are the small size of the wafer, which can support very complex designs, low cost of monolithic mass production, and good customization by users. For the gate array, the master chip is produced in advance, its chip size has been fixed, the resources in the chip are evenly distributed in the chip, and many resources may not be fully utilized. However, for standard cells, only the required standard cells will be placed in the water, so the smaller the size of the wafer, the more the number of wafers that can be cut per wafer, and the lower the cost of a single wafer. This is the advantage of the standard cell structure ASIC in mass production.


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