SiP and Chiplet have become the hottest packaging technology.
Время обновления: 2022-08-08 17:24:04
In the post- Moore's Law era, how to significantly improve the performance of chips without relying on expensive advanced processes has become a common concern in the industry. At this time, the strategic position of packaging in the whole industry is highlighted, from the traditional flip-chip and wafer-level packaging, gradually expanded to fan-out packaging, 3D packaging, SiP (System-in-Package), and other methods. The latter are representative technologies of advanced packaging.
SiP package is called System In a Package, which integrates multiple functional chips, including processors, memories, and other functional chips, into one package to achieve a basic and complete function. SiP is an important path beyond Moore's Law from the packaging perspective. According to the subordination, SoC is a part of SiP. We all know that Apple's Apple Watch and AirPods are both beneficiaries of SiP packaging technology.
As the role of SiP packaging is becoming more and more recognized, the dimensions of manufacturers who are currently laying out have become more diversified, such as foundries and assembly plants in the consumer electronics industry chain, Tier 1 suppliers in the automotive industry chain, traditional semiconductor packaging companies, and so on. So how do manufacturers view and layout SiP packaging technology? And what is the relationship between SiP packaging and Chiplet, a popular technology?
The positioning and effect of SiP packaging technology
Apple started to use SiP packaging technology in the first generation of the Apple Watch and achieved positive results. It is reported that the Apple Watch contains about 900 electronic components in total. Through SiP packaging technology, Apple has integrated CPU, memory, audio, touch, power management, WiFi, NFC, and other independent functional devices. In Apple Watch Series 6, Apple has integrated an Apple A13 application processor and some other functional processors through SiP packaging technology.
So, what kind of applications should use SiP packaging technology? Or what are the directions SiP packaging technology can be applied?
The best feature of SiP packaging technology is the flexibility to design the product according to the requirements. SiP packaging technology is one of the development directions of integrated circuits, which is to achieve a balance of performance, size, and power consumption through advanced packaging technology. Compared with SoC, SoC will have higher integration and electrical performance due to integrating digital and analog components on a die. Still, the cost is getting higher with process refinement. And as the size of a single die becomes larger, the yield of SoCs is also a great challenge.
The two main challenges facing SoCs are precisely the advantages of SiP packages. siP packages enable the separation of digital and analog, the option to use advanced processes for the digital logic part and mature processes for the analog part, lower system costs, and shorter time-to-market cycles."
Comparing SiP package products with ordinary module products, among the advantages of SiP packages are：
-More flexible system design.
-higher space utilization.
The results achieved with SiP packaging are：
-45% reduction in module area.
-Significant reduction in product design.
-Four months earlier time-to-market.
-Increased RF performance.
SiP package development requires three major supports: diverse customers, comprehensive technology, and a large talent pool.
Hybrid bonding technology
In addition to SiP packaging technology, TSMC is introducing advanced packaging solutions. The representative technology is 3DFabric technology, which consists of front-end and back-end technologies, including TSMC-SoIC, CoWoS, and InFO.
The bump pitch changes from 100 microns to 55-36 microns from standard packages to embedded bridges. By the time of the Foveros package, Intel stacks chips together to enable horizontal and vertical interconnects with a bump pitch of roughly 50 microns. In the future, Intel will use Hybrid Bonding technology to plan for a bump pitch of fewer than 10 microns.
Hybrid Bonding technology allows the data interaction between devices no longer need to go through the internal bus and external bus in a large circle, can achieve 'upstairs' and 'downstairs' fast communication so that the on-chip bandwidth to get a huge amount of improvement. Secondly, Hybrid Bonding technology can support the chip to operate at a very high frequency; another point is that Hybrid Bonding technology allows the chip to eliminate organic materials, and the heat dissipation capability has been greatly improved.
Chiplet needs new EDA tools
In the concept of advanced packaging, two branches of the concept of development are particularly important. One is the SiP as mentioned earlier package. The other is Chiplet. Currently, Chiplet's future development route is still under planning. Still, as an extension of advanced packaging, Chiplet, in the eyes of some practitioners, is also considered a SiP technology. Of course, it is still too early to set the tone for the technology during its high-speed foundation building and development phase. However, some of the technical advantages of Chiplet have already been revealed.
Chiplet is the rise of modular SoC. The main advantages include the ability to use smaller chips to obtain higher yields beyond the limits of the photomask; the ability to mix and match small chips at the optimal node of the chip in question; Chiplet has reusability and lower cost and can achieve better performance.
Based on the above advantages and features, Chiplet requires a new EDA design tool capable of achieving several functions.
First, in terms of architecture, the EDA tool for Chiplet needs to achieve system-level connectivity, stack management, and support for hierarchical design.
Secondly, regarding physical implementation, EDA tools for Chiplet need to have a collaborative design environment, enable cross-domain engineering changes, support multi-chip 3D layout planning, and wiring, and have a unified database.
Thirdly, in terms of analysis, EDA tools for Chiplet can complete on-chip and package electromagnetic analysis, support joint simulation of chip packages, allow multi-physics analysis, and can be seamlessly integrated with layout and wiring tools.
Finally, regarding verification, EDA tools for Chiplet support chip process constraints, package manufacturing design rules, chip 3D package constraints, and chip data communication protocols.
In the first half of this year, chip makers Intel, TSMC, and Samsung joined forces with Sunrise, AMD, ARM, Qualcomm, Google, Microsoft, Meta (Facebook), and ten other industry giants to announce the formation of the Chiplet Alliance and the launch of a new universal chip interconnection standard, Uncle.
Chiplet is not a continuation of the advanced process. Many functional units will stay on the process node that best suits it. Chiplet wants to package the chips of different companies' bare dies according to the relevant protocol standards to form a new multifunctional chip. This is the change Chiplet brings to the market, bringing a new methodology for designing chips to the semiconductor industry.
Chiplet will change the original chip industry from design, manufacturing, and packaging to the customer, such an industry chain to a new chain from customer demand to packaging and manufacturing. In the Uncle consortium, there are three companies, Google, Microsoft, and Meta, thinking about how Chiplet should be utilized from the customer's perspective. We are currently seeing Chiplet 1.0, which is just a continuation of SoC. At the same time, Chiplet 2.0 will use small chips to design chips from software to hardware, bringing the chips closer to the market and allowing customers to customize the chips they need.
Write at the end
Currently, in the era of change in the chip industry, beyond Moore's voice is getting louder and louder, SiP technology and Chiplet will be more and more attention, will continue to emerge newer technologies to support the development of advanced packaging, and continue to form an industry-wide standard system, allowing the chip industry to enter a new phase.
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